The present disclosure relates generally to semiconductor device manufacturing, and more particularly to the methods for correction of line-width and line-space deviations in photolithography processes used to print and transfer circuit component and patterns onto a semiconductor device substrate.
The manufacture of semiconductor integrated circuits (ICs) and devices require the use of many photolithography process steps to define and create specific circuit components and circuit layouts onto an underlying substrate layer. Conventional photolithography systems project specific circuit and/or component images, defined by a mask pattern reticle, onto a flat substrate material layer coated with a light sensitive film (photoresist) coating. After image exposure, the film is then developed leaving the printed image of the circuit and/or component on the substrate layer. The imaged substrate is subsequently processed with techniques such as etching and doping to alter the substrate layer with the transferred pattern.
The photolithography manufacturing processes experience challenges when the critical dimensions and CDs (the minimum distances between edges of various types of features critical to the definition of IC performance) approach or drop below the wavelength of the light source used within the photolithography operations. At CDs near or below the light wavelength, typically in the sub-micron range, integrity of the printed image pattern may deviate due to several effects, including optical proximity distortions and chemical processing fluctuations. Manifestation of these effects typically includes line-end shortening, line-ends bridging, and/or line-width variations that may also have some dependency upon the substrate material layer and the local density of the pattern lines. Pattern imaging of certain material layers may be more sensitive to certain manifestations of the optical proximity effect. For example, metal layers are more sensitive to the line-shortening issue because metal contacts and interconnections are often located at line-ends, where line-end extensions of greater than 25 nm (nanometer) may be required to ensure proper and complete formation of the contact and interconnect structures. As devices continue to shrink to a smaller size, metal lines with layer thickness of less than 150 nm and/or metal line-to-metal line spacing of less than 100 nm may be highly sensitive to line-end bridging due to distortions and deviations. Similarly, gate layers of the IC substrate with layer thickness of less than 100 nm and/or gate line spacing of less than 110 nm may be highly sensitive to line-end distortions and deviations. Other active material layers of the device substrate may have other or similar dimensional sensitivities to the line-end distortions and deviations.
To avoid or lessen these and other optical proximity effects, the semiconductor industry has attempted to compensate for them with through the modification of the photolithography mask patterns. Such compensation results with improvements to IC production and device yields, significant manufacturing costs reductions (materials, equipment, manpower) as well as the enabling of the semiconductor fabrication facilities for more aggressive device and process technology generations.
A common compensation technique is generally referred to as optical proximity correction (OPC). Distortions/deviations that are targeted for correction by OPC may include line-end shortening, line-end bridging, line width variations, line corner rounding, line density and line depth of focus. The ultimate goal of OPC is to obtain the capability to produce smaller features within an IC design using given equipment set by enhancing the printability of a mask pattern. The OPC technique applies systematic changes to mask pattern geometries to compensate for the distortions caused by optical diffraction and scattering from the photolithography operations. A mask pattern incorporating OPC is thus a system that negates undesirable distortion effects during pattern transfer. OPC works by making small changes to the IC layout that anticipates the distortions/deviations. Additional features are added to the original mask pattern such that the OPC features are typically sub-resolution (i.e. having dimensions less than the resolution of the light exposing tool) and thus do not transfer onto the device substrate. It is noted that these features interact with the original mask pattern as to improve the final transferred pattern. Such features are commonly known as “serifs”. Serifs are the typically small, appendage-type addition or subtraction regions typically made at the corner, end regions or other areas of the mask pattern designs.
Line-end distortions/deviations are generally more difficult to correct due to concerns with both line-end shortening and line-end bridging issues. These line-related issues are most difficult with line layers and structures that feature line ends that are positioned opposing and/or adjacent to each other in very close proximity. These issues pose challenges to the OPC techniques in that the OPC methods must contend with the tradeoffs of preventing line ends from being transferred as shorter or smaller than the intended designed layout pattern, and the prevention of lines from being transferred as too long or too big, causing unintended bridging or connection to either adjacent or opposite lines. Accordingly, these line end issues are also commonly known as line spacing or line extension issues, referencing respectively, to the criticality of the spacing between the line ends of the individual line structures or to the overall length of the line.
Existing OPC methods for line-ends utilize symmetric OPC structures applied to mask pattern line designs. The technique when applied correctly is an effective technique for correcting the distortions/deviations induced upon line-ends from the optical proximity effects. The added line area from the applied OPC structures will usually require photolithographic and subsequent line-forming etch processes to be more critical and precise to prevent line-to-line bridging as well as excessive line-end shortening. This degradation in the process conditions windows become worsened as the device geometries continue to shrink with newer and future device/process technology generations.
It is desired to have an OPC method that does not require small/tight process operational windows. Such an improved OPC method is also desired to be easily incorporated into existing semiconductor manufacturing operations with minimal additional requirements for the manufacturing engineers and production operators.